Martin Murphy

As contribution to a recent debate (James, 1998; Murphy etal., 1997, 1998) the proportion of twins following ovulation induction (OI) or assisted conception (AC) in 1994 in Oxfordshire and West Berkshire was estimated, and by extrapolation the natural twinning rate in England and Wales was judged to have maintained a plateau phase since the 1970s. Similar figures for 1995 and 1996 from the same study, and hence a more stable local estimate, are now provided. The proportions, as before, were estimated from women's responses to a questionnaire within a case[hyphen]control study, with ascertainment from general practitioners' records or hospital case[hyphen]notes for non[hyphen]responders or for those excluded from the study originally. In 1994, 1995 and 1996 the proportion of twins following OI/AC was overall 27% (24%, 30% and 27% respectively). Restriction to the 87% locally resident made no difference. The national crude twinning rate for those years was overall 13·3 per 1000 maternities (12·8, 13·6 and 13·4 respectively)

As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software cotuning as a novel approach for system design, in which traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multi-processor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency - a key driver for next generation of HPC system design. Copyright 2009 ACM.